1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, to a fine MIS (Metal Insulator Semiconductor) type semiconductor device represented by a MOS (Metal Oxide Semiconductor) transistor, and a method for manufacturing the same.
2. Description of the Prior Art
Heretofore, with the progress in higher integration and higher operating speed of LSIs, MOS transistors have been rapidly made finer. In such a fine semiconductor device, since a gate length is very short, problems have been posed in which a breakdown voltage between a source and a drain is reduced, a threshold voltage is reduced, and a hot carrier resistant-property is reduced. In order to solve these problems, various approaches have been proposed.
As an example, S. Ogura et al. disclose in "IEEE Transactions Electron Devices", ED-16, page 1356, issued in 1980, an LDD (Lightly Doped Drain) type MOS transistor structure in which a source and a drain respectively composed of a low concentration impurity layer and a high concentration impurity layer are formed by reducing an impurity concentration (a low concentration impurity layer is formed) in the vicinity of a gate. This LDD type MOS transistor structure provides an advantage in that the low concentration impurity layer moderates an electric field in the vicinity of the gate, in the source and in the drain, and in that the reduction of a breakdown voltage between the source and the drain, the reduction of a threshold voltage, and the generation of hot carrier are prevented. In this LDD type MOS transistor structure, normally, the low concentration impurity layer is formed in a self-aligned manner by ion implanting of an impurity into a semiconductor substrate by using a gate electrode formed on the semiconductor substrate as a mask, side walls are formed on side surfaces of the gate electrode after the low concentration impurity layer is formed, and the high concentration impurity layer is formed in the self-aligned manner by implanting an impurity into the semiconductor substrate by using the side walls and the gate electrode as a mask.
Furthermore, T. Mizuno et al. disclose in "IEDM Technical Digest", page 613, issued in 1989, that when a material having a higher dielectric constant is used, as side walls which are utilized for forming the low concentration impurity layer and the high concentration impurity layer, the electric field at a gate fringe portion is increased, and the electric field at a drain end is moderated, and as a result, the breakdown voltage between the source and the drain is improved.
However, in the above-mentioned LDD type MOS type transistor structure, a plurality of thermal processes including a thermal process of forming an interlayer dielectric film at a high temperature, and a thermal process of performing reflow of a glass film or the like are need after the low concentration impurity layer and the high concentration impurity layer are formed. As a result, although the LDD type MOS type transistor is structured to prevent the reduction of the breakdown voltage between the source and the drain, the reduction of the threshold voltage and the generation of the hot carrier, a problem arises in which during the thermal processes, the impurities of the low and the high impurity concentration layers are diffused, and an effective channel length is shortened, and the short channel effect appears significantly to the extent that the above-mentioned advantages are diminished.